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SMALL BUSINESS
Tiempo Chooses Verific Design Automation
SystemVerilog Analyzer, Static Elaborator Serve as Front End to New Synthesis Software for Asynchronous Chip Design
Business Wire
Tiempo,
provider of breakthrough, ultra low-power asynchronous intellectual
property (IP) for embedded applications, has chosen
Verific
Design Automation, a de facto industry standard, as the front end
for its software products.
Tiempo licenses Verific
Copyright Business Wire 2009
2009-10-28 11:00:00
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